Integrated circuit devices have long been the building blocks for a wide variety of applications. One of the largest applications for integrated circuits has been in the field of digital computers, where the development of smaller feature sizes for the integrated circuit has allowed for greater capacity and flexibility in operating a digital computer. In particular, the developments in integrated circuits have provided for increased memory capacity and different types of memory devices. One such memory device is the Double Data Rate Dynamic Random Access Memory, referred to as DDR DRAM.
DDR DRAM transfers data at both the rising and falling edge of a clock signal, unlike traditional SDRAM, which transfers data only on the rising edge of a clock signal. In operation, DDR and similar memory devices utilize differential signaling for clock signals at clock pins of a device package. Differential signaling for these clock signals reduces sensitivity to common mode voltages to enable the production of a stable internal timing reference. Typically, a differential signal provides good signal integrity from which a balanced receiver can be built that maintains good duty cycle performance internally. However, DDR and similar memory devices utilize non-differential signaling for data signals input on the device data pins. The received data signals are compared to a voltage reference voltage supplied by the system. The lack of differential signaling for the received data signals introduces sensitivities to both the common mode signal voltage and reference voltage levels. As a result, the received data signals exhibit timing skew relative to the received clock signals, when the signaling levels depart from ideal.
The non-differential signals and their sensitivity to the system voltage reference, VREF, may result in data signal offsets, which requires some compromise in building the receivers used in applications such as memory devices. As a result of these design compromises, the internal signals after capture generally do not have the same duty cycle integrity as the system clock signal. This reduction in duty cycle integrity could be due to several reasons. Imbalances in the memory buffers can occur during wafer processing due to variations between p-type channel devices and n-type channel devices in drive strength that can vary from wafer to wafer. Invariably, the p to n drive strength ratios are not as balanced as initially designed. This variation from the design is a factor when examining the received data signal relative to VREF.
The data signal is examined relative to a trip point of a data receiver. A trip point is essentially the transition point, or transition threshold, at which the data receiver transitions from a one to a zero, that is, the point at which, when the input changes from one level to another, the output changes from one level to another. Ideally, the trip point should be exactly equal to VREF. As the received data signal transitions through the voltage level represented by VREF, the output of the receiver will transition from one state to another. Thus, the data signals are being examined relative to the VREF level in the circuitry of the data receivers using p-type and n-type device elements. With imbalances from the design in the p to n drive strength ratio, the trip point may be somewhat shifted from VREF. As a result, imbalances in a duty cycle may occur, or the rise and fall times of the data signal and that of a data buffer may not be matched as desired. As a result, some timing skews relative to the received clock signal may occur. Then, generally, as data is sent from the data receivers to data latches, any kind of timing skew incurred in the data receivers translates into set-up and hold timing problems.
Generally, VREF is a reference voltage set as one-half the power supply. If data signals swing from VSS to VDD, VREF should be (VDD−VSS)/2. The ideal level for VREF is to be perfectly centered in the signal swing. If VREF is not centered in the signal swing, the output duty cycle from the data receiver can be affected. Further, any noise on the VREF input to the receiver could potentially affect the timing of the output signal in a high speed device. In a high speed device, the design intent is to guarantee certain set up and hold times, such that measured from where the clock makes a transition, there is a certain set up time requirement where data has to be transitioned and settled before the clock transition occurs. At higher frequencies, the set up and hold time is smaller, thus any errors or deviations from design created on the chip die will negatively affect set up and hold times. In addition to making integrated circuits as accurate as possible, there is a need to correct for imbalances in the transistors in the integrated circuit, and correct for DC offsets in the VREF signal.
Typically, once the integrated circuit has been made, data signal offsets and timing skews are not corrected during operation of the processed integrated circuit. A problem dealing with adjusting timing offsets of a digital signal relative to a coincident clock signal has been addressed in U.S. Pat. No. 6,029,250, entitled “Method and Apparatus for Adaptively Adjusting the Timing Offset Between a Clock Signal and Digital Signals Transmitted Coincident with that Clock Signal, and Memory Device and System Using the Same,” and assigned to the assignee of the present invention. In the above patent, a number of digital signals with respective timing offsets are stored and evaluated, where one of the timing offsets from the number of digital signals stored is selected to be used to adjust the timing offsets for the digital signals. Such an approach will not fully address the problems previously discussed. There remains a need for correcting data signaling offsets and timing skews in a data receiver as it operates. The present invention provides a solution to this problem.